1. Field of the Invention
The present invention relates to a semiconductor device with silicide layers and a fabrication method thereof and more particularly, to a semiconductor device equipped with at least two sections necessitating different electric characteristics or performance of built-in electronic elements/circuits, such as a logic circuit section, a Dynamic Random-Access-Memory (DRAM) cell section, a peripheral or control circuit section of DRAM cells, and so on, and a fabrication method of the device.
2. Description of the Prior Art
Conventionally, a semiconductor device equipped with a logic circuit section including logic circuits such as sensing amplifiers and a DRAM cell section including an array of DRAM cells is known, which has been practically used in various application fields. Not only the logic circuits but also the DRAM cells are typically formed by Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs).
In the semiconductor devices of this sort, to increase the operation speed of the logic circuits provided in the logic circuit section, silicide layers of a refractory metal such as tungsten (W), titanium (Ti), molybdenum (Mo), cobalt (Co), and nickel (Ni) need to be incorporated into source/drain regions and gate electrodes of MOSFETs that constitute the logic circuits. This is because the refractory-metal silicide layers are lower in electric resistance than single-crystal silicon (Si) and polysilicon layers.
Typically, the refractory-metal silicide layers are produced by a chemical reaction of a refractory metal with Si during a heat treatment process, which is termed a "silicidation reaction". Therefore, not only the logic circuit section but also the DRAM cell section, which are located on a same silicon substrate, are subjected to the heat treatment process. Thus, the refractory-metal silicide layers are incorporated in the source/drain regions and the gate electrodes of the MOSFETs in both the logic circuit section and the DRAM cell section.
The refractory-metal silicide layers incorporated in the source/drain regions in the DRAM cell section tend to increase the current leakage at the p-n junctions of the relating source/drain regions. Therefore, there arises a problem that the data-storing characteristic or performance of the DRAM cells is degraded.
To solve this problem, a configuration shown in FIG. 1 may be thought. In this configuration, a patterned isolation dielectric 119 is formed on a main surface of a p-type single-crystal Si substrate 101, thereby defining a logic circuit section 120 having n-channel MOSFETs 121 and a DRAM cell section 130 having n-channel MOSFETs 131 and storage capacitors 132. For the sake of simplification of description, one of the MOSFETs 121, one of the MOSFETs 131, and one of the capacitors 132 are shown in FIG. 1, and explanation about only these three elements is presented below.
In the logic circuit section 120, a pair of n.sup.+ -type diffusion regions 109b and a pair of n.sup.- -type diffusion regions 110b are formed in the substrate 101, thereby forming a pair of source/drain regions 104b and 105b with the Lightly-Doped Drain (LDD) structure. One of the two diffusion regions 109b located at the right-hand side and the adjoining diffusion region 110b form the source/drain region 104b. The other of the two diffusion regions 109b located at the left-hand side and the adjoining diffusion region 110b form the source/drain region 105b.
A gate insulating layer 102b is formed on the main surface of the substrate 101 between the pair of n.sup.+ -type diffusion regions 109b. The gate insulating layer 102b is overlapped with the underlying pair of n.sup.- -type diffusion regions 110b. A polysilicon layer 103b and a pair of sidewall spacers 114b are formed on the gate insulating layer 102b. The pair of sidewall spacers 114b are located at each side of the polysilicon layer 103b. Further, a sulicide layer 112b of a refractory metal is formed on the polysilicon layer 103b to be sandwiched by the sidewall spacers 114b. The silicide layer 112b and the polysilicon layer 103b serves as a gate electrode 118b.
The pair of source/drain regions 104b and 105b, the gate insulating layer 102b, the gate electrode 118b, and the pair of sidewall spacers 114b constitute the MOSFET 121.
In the DRAM cell section 130, a pair of n.sup.+ -type diffusion regions 109a and a pair of n.sup.- -type diffusion regions 110a are formed in the substrate 101, thereby forming a pair of source/drain regions 104a and 105a with the LDD structure. One of the two diffusion regions 109a located at the right-hand side and the adjoining diffusion region 110a form the source/drain region 104a. The other of the two diffusion regions 109a located at the left-hand side and the adjoining diffusion region 110a form the source/drain region 105a.
A gate insulating layer 102a is formed on the main surface of the substrate 101 between the pair of n.sup.+ -type diffusion regions 109a. The gate insulating layer 102a is overlapped with the underlying pair of n.sup.- -type diffusion regions 110a. A polysilicon layer 103a and a pair of sidewall spacers 114a are formed on the gate insulating layer 102a. The pair of sidewall spacers 114a are located at each side of the polysilicon layer 103b. Further, a silicide layer 112a of a refractory metal is formed on the polysilicon layer 103a. The silicide layer 112a and the polysilicon layer 103a serves as a gate electrode 118a.
The pair of source/drain regions 104a and 105a, the gate insulating layer 102a, the gate electrode 118a, and the pair of sidewall spacers 114a constitute the MOSFET 131.
Further, an n-type diffusion region 108 is formed in the substrate 101 to be contacted with the n.sup.+ -type diffusion region 109a located at the right-hand side and the isolation dielectric 119. The diffusion region 108 serves as a lower electrode of the capacitor 132. A capacitor dielectric layer 107 is selectively formed on the diffusion region 108. A conductive layer 106 is selectively formed on the isolation dielectric 119 to be contacted with the capacitor dielectric layer 107. The conductive layer 106 serves as an upper electrode of the capacitor 132.
The capacitor 132 is electrically connected to the MOSFET 131 at the contact area of the diffusion regions 108 and 109a.
With the device configuration shown in FIG. 1, since no silicide layer is incorporated in the source/drain regions 104a and 105a of the MOSFET 131 in the DRAM cell section 130, the above-described problem that the data-storing characteristic or performance of the DRAM cells is degraded can be solved. However, in this case, there arises anther problem that the operation speed of the logic circuits (i.e., the MOSFET 121) in the logic circuit section 120 is not satisfactorily high.
Thus, it is necessary to develop a technique enabling the selective silicidation reaction of the source/drain regions in the logic circuit section 120 and the DRAM cell section 130.
An example of the selective silicidation technique is shown in FIGS. 2A to 2C, which is substantially the same as that disclosed in the Japanese Non-Examined Patent Publication No. 1-264257 published in October 1989.
In the conventional selective silicidation technique disclosed in the Japanese Non-Examined Patent Publication No. 1-264257, as shown in FIG. 2C, a patterned isolation dielectric 219 is formed on a main surface of a p-type single-crystal Si substrate 201, thereby defining a logic circuit section 220 having an n-channel MOSFET 221 and a DRAM cell section 230 having an n-channel MOSFET 231 and a storage capacitor 232.
In the logic circuit section 220, a pair of n.sup.+ -type diffusion regions 209b and a pair of n.sup.- -type diffusion regions 210b are formed in the substrate 201 and at the same time, silicide layers 212c of a refractory metal are formed on the n.sup.+ -type diffusion regions 209b. Thus, a pair of source/drain regions 204b and 205b with the LDD structure are formed. One of the two diffusion regions 209b located at the right-hand side, the overlying silicide layer 212c, and the adjoining diffusion region 210b form the source/drain region 204b. The other of the two diffusion regions 209b located at the left-hand side, the overlying silicide layer 212c, and the adjoining diffusion region 210b form the source/drain region 205b. Thus, the silicide layers 212c are incorporated in the source/drain regions 204b and 205b in the logic circuit section 220.
A gate insulating layer 202b is formed on the main surface of the substrate 201 between the pair of n.sup.+ -type diffusion regions 209b. The gate insulating layer 202b is overlapped with the underlying pair of n.sup.- -type diffusion regions 210b. A polysilicon layer 203b and a pair of sidewall spacers 214b are formed on the gate insulating layer 202b. The pair of sidewall spacers 214b are located at each side of the polysilicon layer 203b. Further, in addition to the silicide layers 212c formed on the n.sup.+ -type diffusion regions 209b, a silicide layer 212b is formed on the polysilicon layer 203b to be sandwiched by the sidewall spacers 214b. The silicide layer 212b and the polysilicon layer 203b serves as a gate electrode 218b.
The pair of source/drain regions 204b and 205b, the gate insulating layer 202b, the gate electrode 218b, and the pair of sidewall spacers 214b constitute the MOSFET 221 in the logic circuit section 220.
In the DRAM cell section 230, a pair of n.sup.+ -type diffusion regions 209a and a pair of n.sup.- -type diffusion regions 210a are formed in the substrate 201, thereby forming a pair of source/drain regions 204a and 205a with the LDD structure. One of the two diffusion regions 209a located at the right-hand side and the adjoining diffusion region 210a form the source/drain region 204a. The other of the two diffusion regions 209a located at the left-hand side and the adjoining diffusion region 210a form the source/drain region 205a.
Thus, unlike the MOSFET 221 in the logic circuit section 220, the MOSFET 231 in the DRAM cell section 230 has no silicide layers incorporated in the source/drain regions 204a and 205a.
A gate insulating layer 202a is formed on the main surface of the substrate 201 to cover the pair of n.sup.+ -type diffusion regions 209a. The gate insulating layer 202a is overlapped with the underlying pairs of diffusion regions 209a and 210a. A polysilicon layer 203a and a pair of sidewall spacers 214a are formed on the gate insulating layer 202a. The pair of sidewall spacers 214a are located at each side of the polysilicon layer 203b. Further, a silicide layer 212a is formed on the polysilicon layer 203a. The silicide layer 212a and the polysilicon layer 203a serves as a gate electrode 218a.
The pair of source/drain regions 204a and 205a, the gate insulating layer 202a, the gate electrode 218a, and the pair of sidewall spacers 214a constitute the MOSFET 231 in the DRAM cell section 230.
Further, an n-type diffusion region 208 is formed in the substrate 201 to be contacted with the n.sup.+ -type diffusion region 209a located at the right-hand side and with the adjoining isolation dielectric 219. The diffusion region 208 serves as a lower electrode of the capacitor 232. A conductive layer 206 is selectively formed on the isolation dielectric 219 to be contacted with the gate insulating layer 202a. The conductive layer 106 serves as an upper electrode of the capacitor 232. A part of the gate insulating layer 202a, which is sandwiched by the diffusion region 208 and the conductive layer 206, serves as a capacitor dielectric of the capacitor 232.
The capacitor 232 is electrically connected to the MOSFET 231 at the contact area of the diffusion regions 208 and 209a.
With the device configuration shown in FIG. 2C, since the source/drain regions 204a and 205a and 204b and 205b have the LDD structure, the channel regions of the MOSFETs 221 and 231 are able to be shortened while preventing the bad effects due to the hot carriers from occurring. Also, the gate electrodes 218a and 218b have the polycide structure, so the electric resistance of the gate electrodes 218a and 218b can be decreased, which contributes to the high-speed operation of the MOSFETs 221 and 231.
Moreover, the source/drain region 204a serving as a charge storage node in the DRAM cell section 230 has no silicide layer incorporated therein while the source/drain regions 204b and 205a in the logic circuit section 220 has the silicide layers 212c incorporated therein. Therefore, the parasitic resistance of the source/drain regions 204b and 205a in the logic circuit section 220 can be lowered and at the same time, malfunction due to the junction current leakage can be prevented from occurring.
The device configuration shown in FIG. 2C is fabricated in the following way.
First, as shown in FIG. 2A, the isolation dielectric 219 is formed on the substrate 201 to define the logic circuit section 220 and the DRAM cell section 230, and then, the gate insulating layers 202a and 202b are formed on the main surface of the substrate 201 in the two sections 220 and 230. Next, polysilicon and silicon nitride (Si.sub.3 N.sub.4) are deposited successively by Chemical Vapor Deposition (CVD) processes on the gate insulating layers 202a and 202b. Then, the deposited polysilicon and Si.sub.3 N.sub.4 are patterned to form the polysilicon layers 203a and 203b located respectively on the gate insulating layers 202a and 202b, and Si.sub.3 N.sub.4 layers 213a and 213b located respectively on the polysilicon layers 202a and 202b. The state at this stage is shown in FIG. 2A.
Subsequently, using the polysilicon layers 203a and 203b as a mask, the pair of n.sup.- -type diffusion regions 210a are formed in the substrate 201 at each side of the polysilicon layer 203a in the DRAM cell section 230 and the pair of n.sup.- -type diffusion regions 210b are formed in the substrate 201 at each side of the polysilicon layer 203b in the logic circuit section 220 by an ion-implantation process, as shown in FIG. 2B. The n.sup.- -type diffusion regions 210a are in self-alignment to the polysilicon layer 203a. The n.sup.- -type diffusion regions 210b are in self-alignment to the polysilicon layer 203b.
After a silicon dioxide (SiO.sub.2) layer (not shown) is formed to cover the whole substrate 201 by a CVD process, the SiO.sub.2 layer thus formed is patterned by a Reactive Ion Etching (RIE) process, thereby forming the pair of sidewall spacers 214a on the gate insulating layer 202a and the pair of sidewall spacers 214b on the gate insulating layer 202b. The pair of sidewall spacers 214a are located at each side of the polysilicon layer 203a, and the pair of sidewall spacers 214b are located at each side of the polysilicon layer 203b.
Using the polysilicon layers 203a and 203b and the sidewall spacers 214a and 214b as a mask, an n-type dopant is introduced by an ion-implantation process into the substrate 201 to be overlapped with the n.sup.- -type diffusion regions 210a and 210b, thereby forming the pair of n.sup.+ -type diffusion regions 209a at each side of the polysilicon layer 203a in the DRAM cell section 230 and the pair of n.sup.+ -type diffusion regions 209b at each side of the polysilicon layer 203b in the logic circuit section 220, as shown in FIG. 2B. The n.sup.+ -type diffusion regions 209a are in self-alignment to the polysilicon layer 203a and the sidewall spacers 214a. The n.sup.+ -type diffusion regions 209b are in self-alignment to the polysilicon layer 203b and the sidewall spacers 214b.
After the Si.sub.3 N.sub.4 layers 213a and 213b located on the polysilicon layers 203a and 203b are removed, the gate insulating layer 202b existing in the logic circuit section 220 is selectively removed, thereby exposing selectively the main surface of the substrate 201, i.e., the surfaces of the n.sup.+ -type diffusion regions 209b. Then, a refractory metal layer (not shown) is formed to cover the whole substrate 201 by a sputtering process, in which the refractory metal layer is contacted with the surfaces of the n.sup.+ -type diffusion regions 209b. The substrate 201 with the refractory metal layer is subjected to a heat treatment process at approximately 600.degree. C. to cause a silicidation reaction between the substrate 201 made of Si and the refractory metal layer. Thus, the silicide layers 212c are respectively formed on the n.sup.+ -type diffusion regions 209b and at the same time, the silicide layers 212a and 212b are respectively formed on the polysilicon layers 203a and 203b, as shown in FIG. 2C.
After the unreacted refractory metal layer is removed, finally, the substrate 201 with the silicide layers 212a, 212b, and 212c is subjected to a heat treatment process again at approximately 900.degree. C., thereby causing a phase transition of the layers 212a, 212b, and 212c. As a result, the electric resistance of the silicide layers 212a, 212b, and 212c is lowered.
Through the above-described process steps, the device configuration as shown in FIG. 2C is obtained, in which the MOSFET 231 in the DRAM cell section 230 has no suicide layers incorporated in the source/drain regions 204a and 205a while the MOSFET 221 in the logic circuit section 220 has the silicide layers incorporated in the source/drain regions 204b and 205b.
With the fabrication method of the conventional device configuration shown in FIG. 2C, as seen from the above explanation, the gate insulating layer 202a in the DRAM cell section 230 is used as a masking layer for preventing the silicidation reaction from occurring at the n.sup.+ -type diffusion regions 209a during the silicidation process of the refractory film. Taking this masking purpose into consideration, the gate insulating layer 202a needs to have a thickness of approximately 100 .ANG. or greater. On the other hand, the gate insulating layer 202a becomes thinner with the progressing miniaturization of the semiconductor device.
Therefore, there arises a problem that the gate insulating layer 202a tends to become unable to accomplish the desired masking purpose dependent upon the progressing miniaturization. If so, the n.sup.+ -type diffusion regions 209a in the DRAM cell section 230 tend to be silicided, resulting in increase in junction current leakage. This problem is referred as the first problem later.
Moreover, the fabrication method of the conventional device configuration shown in FIG. 2C has second and third problems explained below. Specifically, this fabrication method includes the process of removing selectively the gate insulating layer 202b in the logic circuit section 220. Typically, a photolithography technique is used for this selective removing process.
Also, if the source/drain regions 204a and 205a in the DRAM cell area 230 and the source/drain regions 204b and 205b in the logic circuit section 220 are planned to be separately formed, the DRAM cell area 230 will be covered with a photoresist film when the source/drain regions 204b and 205b are formed in the logic circuit section 220. Subsequently, the logic circuit section 220 will be covered with another photoresist film when the source/drain regions 204a and 205a are formed in the DRAM cell section 230.
Accordingly, there is the second problem that the number of the necessary photolithography processes is as much as four in total.
Additionally, most of the patterns located in the logic circuit section 220 are isolated ones while most of the patterns located in the DRAM cell section 230 are line-and-space ones. Therefore, these two sections 220 and 230 have different optimum exposure conditions for the processes to expose the photoresist films.
As a result, in the fabrication method of the conventional device structure shown in FIG. 2C where both the two sections 220 and 230 are exposed in a same process, there is the third problem that the gate electrodes 218a and 218b tend to be difficult or unable to be formed at a desired high accuracy with the progressing miniaturization of the semiconductor device.
Additionally, the Japanese Non-Examined Patent Publication No. 9-64294 published in March 1997 discloses a fabrication method of a semiconductor device with a DRAM cell section and a peripheral circuit section. However, this Publication discloses only the technique that silicide layers are incorporated in the source/drain regions of MOSFETs located in the peripheral circuit section while no silicide layers are incorporated in the source/drain regions of MOSFETs located in the DRAM cell section. This Publication discloses no way to incorporate the silicide layers in the source/drain regions of the MOSFETs located in the DRAM cell section and the peripheral circuit section.
As a result, the conventional method disclosed in the Japanese Non-Examined Patent Publication No. 9-64294 is unable to solve the above-described first to third problems.
The Japanese Non-Examined Patent Publication No. 9-181269 published in July 1997 discloses a fabrication method of a semiconductor device with a DRAM cell section and a logic circuit section. This Publication shows the technique that silicide layers are incorporated in the source/drain regions of MOSFETs and the gate electrodes thereof, including bit lines, in the logic circuit section. However, this Publication shows only the technique that silicide layers are incorporated in the bit lines in the DRAM cell section.
As a result, the conventional method disclosed in the Japanese Non-Examined Patent Publication No. 9-181269 is unable to solve the above-described first to third problems because of the complicated process sequence and the large number of necessary process steps.